vhdl - Behavioural logic sequential, code cannot work? -


basically have following code in module. want change number it's 2's complement negative.

eg. 100 becomes -100, , -200 becomes 200.

a shortcut found read lsb until reach '1', flip bits after it. i'm trying implement 32 bit converter using least performance tradeoff (i heard num <= not(num) + 1 quite resource heavy)

                flipbit <= '0'; -- reset flip bit                 in 0 31 loop                     if flipbit = '1'                         tempsubtract(i) <= not operand2(i);                     else                         tempsubtract(i) <= operand2(i);                     end if;                     if operand2(i) = '1'                         flipbit <= '1';                     end if;                 end loop;

however, not entire thing. also, when num <= not(num)+1, slow way, gives me gibberish numbers too.

can tell me what's wrong? thanks.

this synthesis tool can better you, recommend use z <= -a;, a , z of type signed.

this cause synthesis optimize negation target architecture, no matter is. example, calculating not + 1 in fpga efficient.


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