In Makefile how do I build seperate executable for each C file -
i using check c unit tests. each c library file create there should 1 test file should generate single executable linked test , source code. executable should run make sure tests pass.
when there 1 test file , 1 source file works great. add second source file corresponding test file, tries link them 1 executable.
how second rule pull 1 test_src , matching src , header file test_obj compile 2 object files executable? below current makefile
out_dir=bin build_dir=build test_build_dir=test_build src_dir=src test_src_dir=tests src= $(wildcard $(src_dir)/*.c) test_src= $(patsubst $(src_dir)/%.c, $(test_src_dir)/%_tests.c, $(src)) test_obj= $(patsubst $(test_src_dir)/%.c, $(test_build_dir)/%.o, $(test_src)) obj= $(patsubst $(src_dir)/%.c, $(build_dir)/%.o, $(src)) $(out_dir)/string_calculator_tests: $(test_obj) gcc -o $@ $^ `pkg-config --cflags --libs check` $(test_obj): $(test_src) $(src) gcc -c -o $@ $^ `pkg-config --cflags --libs check`
any appreciated.
it's little unclear how want makefile behave, can take in stages.
look @ rule:
$(test_obj): $(test_src) $(src) gcc -c -o $@ $^ `pkg-config --cflags --libs check`
each object built out of all source files. , don't seem have rule obj
. let's replace 2 static pattern rules:
$(test_obj): $(test_build_dir)/%.o : $(test_src_dir)/%.c gcc -c -o $@ $< `pkg-config --cflags --libs check` $(obj): $(build_dir)/%.o : $(src_dir)/%.c gcc -c -o $@ $< `pkg-config --cflags --libs check`
then rule build executable pair of object files:
tests = $(patsubst $(src_dir)/%.c, $(test_build_dir)/%_test, $(src)) $(tests): $(test_build_dir)/%_test : $(build_dir)/%.o $(test_build_dir)/%_tests.o gcc -o $@ $^ `pkg-config --cflags --libs check`
then rule build tests:
.phony: all_tests all_tests: $(tests)
that should enough started. once works, there many possible improvements, such targets run tests, , tidier ways write tests using advanced techniques vpath
. , haven't talked header files , dependency handling...
Comments
Post a Comment