gnu make multiple targets one object each -


i have old project i'm trying create multiple binaries, 1 each object in directory. cannot life of me figure out how deal multiple targets in manner. following works, seems me should able have 1 rule link them all, speak,

 # compile objects, no problem  %.o: %.c      $(cc) -c $(cflags) $(cppflags) $< -o $@   bin: bin.o      $(cc) -o $@ $< ../lib/libfoo.a -lm $(arch)   bar: bar.o     $(cc) -o $@ $< ../lib/libfoo.a -lm $(arch)

one approach did work strip off suffix target name this, , compile , link in 1 step, feels little hackish,

 %.o: %.c     $(cc) $(cflags) $(cppflags) $< ../lib/libfoo.a -lm -o $(*f)

disclaimer: despise make

update 1: ended with

 execs = bin bar ...   all: $(execs)   %: %.c       @echo "building $@ $<"       $(cc) -c $(cflags) $(cppflags) $< -o $@.o       $(cc) $(cflags) $(cppflags) $@.o ../lib/libfoo.a -lm -o $@

the convention have @ top of makefile:

.phony: all: bin bar

thus make all make bin , bar, , putting @ top it's default target make without arguments. .phony: documents "metatarget", instructs make run if there happens file called all fresh datestamp.

%: %.o      $(cc) -o $@ $< ../lib/libfoo.a -lm $(arch)

this tells make how make them both.


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