c++ - Makefile for compiling different "modules" which can include each other -

we have project module structure this:

- project   - mod1     - mod1.cpp     - mod1.h     - main.cpp   - mod2     - mod2.cpp     - mod2.h     - main.cpp   - more modules 

the main.cpp file in each module instantiates , tests module. 1 module can include , use module. example, module 1 can include module 2 , other modules.

we want create makefile compiles , includes correct modules , main.cpp file. if write "make module2" makefile compile mod2.cpp, main.cpp (in module 2) , include mod2.h. if write "make module1" makefile compile mod2.cpp, mod1.cpp main.cpp (in module 1) , include mod1.h , mod2.h.

my experience makefiles modest, , i've used several days on without success. making generic preferable adding new module not require major changes makefile.

the closest solution got this:

.phony: clean  flags=-std=c++11 -g -i"$(systemc_path)/include" -i"$(systemc_path)" -l"$(systemc_path)/lib-linux64" -lsystemc $(addprefix -i, $(wildcard src/*))  srcs_without_main= $(filter-out %main.cpp, $(shell find src -name '*.cpp')) target_objs=$(subst src, .build/obj, $(subst .cpp,.o,$(srcs_without_main)))  all: $(filter-out unit_test, $(subst src/, ,$(wildcard src/*)))  .secondary:  .build/obj/%.o: src/%.cpp     @mkdir -p $(shell dirname $@)     g++ $(flags) $^ -c -o $@  clean:     @rm -r .build   %: $(target_objs) .build/obj/%/main.o     @mkdir -p $(shell dirname .build/bin/$@)     g++ $(flags) $^ -o .build/bin/$@ 

srcs_without_main holds cpp files of modules except main files. target_objs corresponding list of object files. % target matches on, example "mod1" compiles cpp files , main.cpp of mod1.

the problem is, segfaults while running after compiling, , need "make clean && make" work again. 1 day used 4 hours debugging code find out makefile kind of broken. on project uses "make clean && make" time in fear of going through same did...

does know clever way this? way: systemc project.

here crude effective makefile job:

cc=g++  vpath %.h mod1 mod2  module1: mod1.o mod2.o main1.o     $(cc) $^ -o $@  module2: mod2.o main2.o     $(cc) $^ -o $@  mod1.o: mod1/mod1.cpp mod1.h mod2.h  mod2.o: mod2/mod2.cpp mod1.h mod2.h  main1.o: mod1/main.cpp mod1.h mod2.h  main2.o: mod2/main.cpp mod1.h mod2.h  %.o:     $(cc) -c $< -o $@ 

note:

1. it puts object files (e.g. mod1.o) in parent directory, presume makefile is.
2. names 2 "main" object files "main1.o" , "main2.o". having 2 files same name in same codebase asking trouble.
3. further refinements possible; designed simplicity.