vhdl - convert a std_logic_vector INPUT to IEEE Float type -


how convert std_logic_vector input of entity in ieee float type, operations in process? entity need receive ieee float of a/d converter.

vhdl doesn't have float type default - has real not synthesisable.

however, ieee-standardised vhdl floating-point types synthesisable.

you'll have cast std_logic_vector unsigned or signed vector first , convert suitable floating-point type, need not ieee-754 defined type


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